The present disclosure relates to a circuit for testing word lines of a semiconductor memory device, and more particularly to a circuit for testing word lines of a semiconductor memory device that is capable of effectively detecting off-leakage due to a drop of the threshold voltage when activating a word line of a semiconductor memory device.
In general, with the increasing integration and speed of a semiconductor memory device, various efforts to devise technologies and devices for storing a large amount of information in a small area are being made. In particular, high integration, low power consumption, and high speed of a semiconductor memory device are accomplished by the design of circuits and lines, and new conceptual circuit configurations.
In the initial period of developing a semiconductor memory device, the area of peripheral circuits in the memory device is larger than that of a cell array in the core region. However, as the semiconductor device is developed, the cell array occupies most of the semiconductor memory device.
This tendency increases with higher integration of memory devices. With higher integration of semiconductor memory devices, a memory cell structure is changed and thus the distance between adjacent gates decreases. Accordingly, when a word line is turned on, adjacent word lines are influenced and off-leakage due to the drop of a threshold voltage occurs. The off-leakage due to the drop of the threshold voltage increases in the cells formed by different processes. Accordingly, a failure may occur upon a package test or reliability test.